VLSI Engineer · Digital Design · Verification
RTL design using Verilog & SystemVerilog. Strong understanding of FSMs, pipelines, and timing.
Functional verification using UVM methodology, testbench creation, and debugging.
Hands-on with EDA tools for synthesis, simulation, synopsis tools,and waveform analysis.
Basic knowledge of floorplanning, placement, routing, and timing closure.
Focused on VLSI Design, Digital Electronics and Embedded Systems.
Strong foundation in Mathematics, Physics, and problem-solving.
Completed training in RTL Design, Verification, and ASIC flow.
Listening and relaxing with music.
Enjoy logical puzzles and coding challenges.
Team sports and outdoor activities.
Looking for opportunities in VLSI Design & Verification.